In semiconductor integrated circuits the integration density becomes high and higher, accompanied by demand for an ultra high speed and an ultra high integration density. Already at present, the integration density for integrated circuits consuming a large amount of electric power because of high speed drive is being limited by the limit of heat evacuation.
However electric power consumption per chip is increased rapidly, accompanied by demand for increasing the performance and the speed of semiconductor circuits. Almost all consumed electric power is transformed into heat and produced heat raises the temperature of a whole chip, which causes deterioration in characteristics of elements and lowering in reliability.
However, by the cooling technique using a present structure, heat evacuation is about 30W/cm.sup.2 by water cooling and a new technique for removing rapidly heat produced within a semiconductor chip to the exterior is required. In a prior art heat current circuit for heat evacuation, the part, at which heat conducting characteristics are the worst, is a heat conducting portion from a wall of solid to cooling medium (air, water).
FIG. 15 represents a heat current circuit in an integrated circuit by the prior art technique, using heat resistance and heat capacity. The figure represents a heat current circuit in an integrated circuit having e.g. a chip thickness of about 500 .mu.m and a chip size of about 1 cm.sup.2 and the meaning of Rf, Rp, Cp, Rsi, Csi and Rb is as follows:
Rf: heat resistance to heat conduction from the front side of the chip, PA0 Rp: heat resistance to heat conduction in a passivation film on the front side of the chip (thickness of about 5 .mu.m), PA0 Cp: heat capacity of the passivation film (negligible in a stationary state), PA0 Rsi: heat resistance to heat conduction in an Si substrate (thickness of about 494 .mu.m), PA0 Csi: heat capacitance of the Si substrate (negligible in a stationary state), and PA0 Rb: heat resistance to heat conduction from the front side of the chip.
FIGS. 16A and 16B show a concrete example of an equivalent circuit of a heat current circuit in a stationary state, in the case where the passivation film used by the prior art technique is made of SiO.sub.2, FIG. 16A representing a case where the front surface is cooled by natural convection and the rear surface by forced air cooling, FIG. 16B representing a case where the front surface is cooled by natural convection and the rear surface by water cooling. In the stationary state heat capacity can be neglected. Representative experimental values of the prior art technique are used for boundary conditions and the heat resistances converted from heat conductivity by force air cooling=0.2W/cm.sup.2 .multidot.K, heat conductivity by water cooling=1W/cm.sup.2 .multidot.K and heat conductivity by natural convection=1.times.10.sup.-3 W/cm.sup.2 .multidot.K are indicated.
As clearly seen from FIGS. 16A and 16B, by the prior art heat evacuating technique, although within the solid of the semiconductor chip the heat resistance is sufficiently low, order of 10.sup.-2 K/W, the heat resistance to the cooling medium is about 5K/W by forced air cooling and about 1K/W by water cooling, which are higher by almost 2 orders of magnitude than that obtained for the solid.
Further e.g. D. B. Tuckerman and F. Pease (IEEE Electron Device Lett., Vol. EDL-2, No. 5, pp 126-129, May 1981, "High Performance Heat Sinking for VLSI") have indicated that it is possible to deal with an extremely high heat production density by forming microchannels of about 50 .mu.m.times.300 .mu.m in a comb shape directly on the rear surface of the Si substrate, through which water is made flow.
However, by this method, since the microchannels are formed by processing directly the Si substrate, there are a number of problems in the fabrication from the practical point of view.
As described above, by the prior art heat evacuating technique, since the heat resistance from the cooling fins to the cooling medium is too high, the cooling fins cannot effect heat evacuation with a high efficiency.
Further, by the method, by which the microchannels are formed in the silicon substrate, there is a problem in the fabrication in practice.